1. Field of the Invention
The present invention generally relates to integrated circuit chip design and more particularly to an improved process for placing items within a chip design that utilizes unused white space to increase yield.
2. Description of the Related Art
Conventional chip design procedures follow a flow similar to that shown in FIG. 1. First, chip physical design is initiated 10. This includes reading chip netlist and technology data. Next, the chip is floorplanned 11 and detailed placement of logic is finalized 12. Next, power routing is finalized 13. Then signals are routed 14 and finally the design is verified 15. The foregoing processes are well-known to those ordinarily skilled in this art field and are not discussed in detail so as not to obscure the salient features of the invention.
Each logic cell placed during the creation of the floorplan 11 is typically designed to minimum design groundrules in order to optimize total chip area during placement of logic devices. However, using very small minimum groundrule cells may negatively impact yield because smaller devices and wires are more likely to be affected by smaller particles of foreign matter. A typical manufacturing environment contains more smaller foreign matter particles than larger particles, which allows larger wires and larger devices (which are not adversely affected by the smaller particles) to have a higher yield (and higher reliability). Further, during the placement of logic devices, there often exists whitespace (areas of the design that do not have any cells) that is not used. Therefore, there is a need for a design process that utilizes such whitespace in an efficient and automated manner to increase yield.
It is, therefore, an object of the present invention to provide a structure and method for improving yield during physical chip design that comprises identifying non-critically timed minimum groundrule cells located within the chip design, determining if whitespace exists around the non-critically timed minimum groundrule cells, and replacing the non-critically timed minimum groundrule cells that have the whitespace with non-minimum groundrule cells if the replacing leaves the functionality of the circuit unaltered. Thus, while the invention may alter the timing somewhat, it does not alter the timing enough to alter the functionality of the circuit.
The invention calculates incremental timing effects caused by replacing each of the non-critically timed minimum groundrule cells with non-minimum groundrule cells, and incrementally returns selected ones of the non-critically timed minimum groundrule cells in place of the non-minimum groundrule cells in the chip design if the incremental timing effects indicate that the replacing produces unacceptable circuit timing changes. The invention only replaces the non-critically timed minimum groundrule cells with the non-minimum groundrule cells if enough space is available to accommodate the non-minimum groundrule cells. A determination of whether enough whitespace is available is made based upon a comparison of the whitespace to a library of the non-minimum groundrule cells containing cell size information.
The timing of the circuit is considered xe2x80x9cunalteredxe2x80x9d if the circuit has a similar timing performance with the non-critically timed minimum groundrule cells and the non-minimum groundrule cells. In addition, the non-critically timed minimum groundrule cells are physically smaller and have a lower manufacturing yield than the non-minimum groundrule cells. The invention increases chip yield by decreasing the number of lower-yielding cells (minimum groundrule cells) and increasing the number of higher-yielding cells (non-minimum groundrule cells).